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silego technology, inc. rev 1.00 000-0055031-100 revised september 21, 2017 greenfet tm low voltage gate driver SLG55031 overview the SLG55031 n-channel fet gate driver is used for controlling the ramping slew rate of the source voltage on n-channel fet switches from a cmos logic level input. intended as supporting control elements for switched voltage rails in energy efficient advanced power management systems, these devices also inclu de circuits to discharge op ened switched voltage rails. SLG55031 uses an external resistor connected between the cnfg pin and gnd to establish the slew rate. f SLG55031 ramps v s from 10% to 90% of 1.50v in 33 s with external resistor = 560k block diagram pin configuration features ? drain voltage range 0.7v to 1.5v ? controlled load discharge rate ? controlled turn on slew rate ? pb-free / rohs compliant ? halogen-free ? 2mm x 2mm tdfn-8 package applications ? low transient load switching ? personal computers and servers ? hot plugging applications ? power rail switches s load 7 gate 6 source 2 4 enable g + _ cc 5 drain 1 timing & logic slg5ap03x 8 done 3 cnfg d drain gnd 3 4 source gate done cnfg 2 3 6 7 8 SLG55031 tdfn-8 enable vcc 1 4 5
000-0055031-100 page 2 of 12 SLG55031 pin description pin name pin number type pin description vcc 1 power supply voltage 5v enable 2 input cmos logic level. high true for SLG55031 cnfg 3 input resistor or capacitor co nnection for timing configuration gnd 4 gnd ground. drain 5 input fet drain connection source 6 input source connection gate 7 output fet gate drive done 8 output output cmos open drain - power good, indicates external fet fully on. ordering information part number external timing component enable polarity external fet threshold voltage range package type SLG55031vtr external resistor high true active 1.5v < vt < 2.5v tdfn-8 - tape and reel (3k units)
000-0055031-100 page 3 of 12 SLG55031 absolute maximum conditions parameter min. max. unit v cc to gnd -0.3 6.0 v voltage at logic input pins -0.3 6.0 v current at input pin -1.0 1.0 ma storage temperature range -65 150 c operating temperature range 0 70 c junction temperature -- 150 c moisture sensitivity level 1 electrical characteristics (-10 c to 75 c) symbol parameter condition/note min. typ. max. unit v cc supply voltage 4.75 5.0 5.25 v i q quiescent current enable = 1, v g not ramping 1.5 5 a i stby standby current enable = 0 2 3 a t operating temperature 0 25 70 c v d driven fet drain voltage may dynamically vary 0.7 -- 1.5 v v g gate voltage tracks supply v cc 4.75 5.0 5.25 v t vt fet turn on delay fet vt <2.0v fet gate cin < 4nf 38-- s i discharge internal discharge equiva- lent current discharges mosfet source -- -- 10 ma v ih high-level input voltage enable pin 2.0 -- -- v v il low-level input voltage enable pin -- -- 1.0 v i ih high-level input current digital pins, v in = v cc -1.0 -- 1.0 a i il low-level input current digital pins, v in = 0v -1.0 -- 1.0 a v oh_logic done pull-up voltage open dr ain output buffer -- -- 5.5 v
000-0055031-100 page 4 of 12 SLG55031 description in a typical application, de-asserting enable turns off the extern al power n-fet. the voltage at the load is discharged through the discharge control path internal to the SLG55031. the rate of discharge is current limited to 10ma. when enable is asserted, gate voltage is applied to the gate of the external power n-fet within 10 s (typical) then the gate voltage is ramped up to v cc - v d (3.5v typical) at a slew rate determined by th e value of the external resistor or capacitor connected to the cnfg pin of the sl g55031. monotonic rise of the external fet?s source voltage v s is maintained even as source current increases after the load device turn on threshol d voltage is reached. after the source voltage has ramped up to the drain voltage ? the voltage drop contribution by r ds-on of the fet, the external fet is fully on and the open drain done signal is asserted. if a voltage is not present on the drain sense pin prior to asse rtion of enable, the fet?s gate will be immediately driven high turning the fet fully on. done may be used as the enable control of a second slg 55031 connected in series thereby providing power on sequence control of a number of switched power rails, or used in a ?wired and? with other done signals to indicate all switched power ra ils are in a power good condition. configuration options the SLG55031 is configured with external passive devices to se lect between two widely separate ramp slew rates. see the following table for details . configuration pin usage table resistor to ground (SLG55031) to 1.5v rail value ( ) 400k 560k 750k typical slew time ( s) 23 33 45
000-0055031-100 page 5 of 12 SLG55031 timing diagram - initial p-on v cc to the SLG55031 must reach v cc min (4.75v) before the device wil l begin to be operational. enable 1 must be asserted 100 s after 100% of v cc has been attained. if v_drain is present at a minimum of 3 s prior to assertion of the enable, the source will begin to ramp towards v_drain after t_vt (10 s typically), the time required for the gate of the fet to be past turn on threshold (typically 2.0v). carefully ex amine specific fet turn-on threshold as we ll as fet c-in and if the values fall outs ide of the range of values covered in the electr ical specifications section of this document, consult silego for applications assis tance in determining the value of t_vt. diagram 1 enable after vcc vcc enable v_drain v_gate v_source done high true example t_vcc_to_en t_drain_to_enable t_vt t_slew
000-0055031-100 page 6 of 12 SLG55031 if v_drain is not present prior to the assertion enable, the driven fet will be turned on immediately following assertion of enable and subsequent application of a volta ge on the drain of the fet will be directly applied to the source (diagram 2). again, v cc must have reached v cc-min before enable will operate the device. v_gate will be pulled to v cc after which the v_source will track the voltage applied to the drain of the fet. 1 t_v cc to enable = 100 s assertion delay (when v cc initially ramping up to 100% of v cc ). 2 enable assertion transition time must be less than 1 s. * if v_drain = 0v prior to assert ion of enable, done becomes true co-incident with assertion of enable. * in the case of v_drain after enable, the def inition of arrival and ramp time are not valid diagram 2 vcc enable v_drain v_gate v_source done* high true example t_vcc_to_en en_to_drain t_slew = drain slew
000-0055031-100 page 7 of 12 SLG55031 timing diagram - rail switching the two components of the fet turn-on time consist of the time it takes to drive the fet?s gate up to turn-on threshold (t_vt) added to the time it takes for the fet?s source voltage to ramp (t_slew) up fully on into the dr iven load. the timing diagram a nd table below show the min/max values for these two component s vs. different rail source voltage. the t_vt delay is 8 s - 10 s typically (with fet vt = 2.0v) depe nding on the threshold voltage of the fet being driven (diagram 3). the table below and diagram 3 illustrate source voltage ramp ti mes for various slew rates and resulting total turn on time (enable to done) when using the SLG55031 for several selected ranges of drain voltages.. (see diagram 4 below for more details) * t_slew: as v_source increases from 10% to 90% of v_drainl; e.g. ramp time ** t_done: from assertion of enable to v_source = 90% of v_drain; e.g. arrival time diagram 3 min ( sec) typ ( sec) max ( sec) SLG55031 r_ext = 560k v_drain voltage (fet vt = 1.5v to 2.5v) 1.35v 1.50v t_slew* 20 30 33 t_done** 42 46 65 recommended fet: on semi ntmfs4834n enable done high true example t_slew t_vt v s t_discharge
000-0055031-100 page 8 of 12 SLG55031 timing definition of arrival time and ramp time 1 the definition of arrival time and ramp time is only valid for enable (asserted with a 100 s delay) after v cc has reached 100% and v_drain is present prior to assertion of enable diagram 4 vcc 5v 100us (min.) 1/2venable 0v enable active high 1us (max) ramping rate for SLG55031v source ramping 90% output rail 0v SLG55031v < 65us SLG55031v 1.35 / 1.5v arrival time 1 enable to 90% output rail timing for vcc and enable 100us (min.) 0v min. ramp time of 10% - 90% output rail must be not less than 20us for SLG55031v ramp time 1 10% ? 90% output rail > 20us 3.3v 90% 10% 90%
000-0055031-100 page 9 of 12 SLG55031 package top marking system definition part id assembly code datecode lot revision 8 7 6 5 1 2 3 4 ? part id field: identifies the specific device configuration ? assembly code field: assembly location of the device. ? date code field: coded date of manufacture ? lot code: designates lot # ? revision code: device revision xx a dd l r
000-0055031-100 page 10 of 12 SLG55031 package drawing and dimensions 8 lead tdfn package note: bottom side metal plate is at ground potential
000-0055031-100 page 11 of 12 SLG55031 tap e and reel specifications carrier tape drawing and dimensions recommended reflow soldering profile please see ipc/jedec j-std-020: latest revision for reflow profile based on package volume of 3.00 mm 3 (nominal). more information can be found at www.jedec.org. package type # of pins nominal package size [mm] max units reel & hub size [mm] leader (min) trailer (min) tape width [mm] part pitch [mm] per reel per box pockets length [mm] pockets length [mm] tdfn 8l green 8 2 x 2 x 0.75 3,000 3,000 178 / 60 100 400 100 400 8 4 package type pocket btm length pocket btm width pocket depth index hole pitch pocket pitch index hole diameter index hole to tape edge index hole to pocket center tape width a0 b0 k0 p0 p1 d0 e f w tdfn 8l green 2.3 2.3 1.05 4 4 1.55 1.75 3.5 8 p1 w e p0 a0 d0 y y b0 k0 section y-y c l f
000-0055031-100 page 12 of 12 SLG55031 silego website & support silego technology website silego technology provides online support via our website at http://www.silego.com/ .this website is used as a means to make files and information easily available to customers. for more information regarding silego green products, please visit: http://greenpak.silego.com/ http://greensak.silego.com/ http://greenlib.silego.com/ http://greenfet.silego.com/ http://greenclk.silego.com/ http://greenddr3.silego.com/ products are also available for purchase directly from silego at the silego online store at http://store.silego.com/ . silego technical support datasheets and errata, application notes and example designs, user guides, and hardware support documents and the latest software releases are available at the sil ego website or can be r equested directly at info@silego.com . for specific greenpak design or applications ques tions and support please send email requests to greenpak@silego.com users of silego products can receive assistance through several channels: online live support silego technology has live video technical assistance and sales support available at http://www.silego.com/ . please ask our live web receptionist to schedule a 1 on 1 traini ng session with one of our application engineers. contact your local sales representative customers can contact their local sales re presentative or field application engineer (fae) for support. local sales offices are also available to help customers. more information regarding your lo cal representative is available at the silego website or send a request to info@silego.com contact silego directly silego can be contacted directly via e-mail at info@silego.com or user submission form, located at the following url: http://support.silego.com/ other information the latest silego technology press releases, listing of seminars and events, listings of world wide silego technology offices a nd representatives are all available at http://www.silego.com/ this product has been designed and qualified for the consumer market. applications or uses as critical components in life support devices or systems are not author ized. silego technology does not assume any liability arising out of such appli- cations or uses of its products. silego technology reserves the right to im prove product design, f unctions and reliability without notice .

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